Hare: a file system for non-cache-coherent multicores

Hare is a new file system that provides a POSIX-like interface on multicore processors without cache coherence. Hare allows applications on different cores to share files, directories, and file descriptors. The challenge in designing Hare is to support the shared abstractions faithfully enough to run applications that run on traditional shared-memory operating systems, with few modifications, and to do so while scaling with an increasing number of cores. To achieve this goal, Hare must support features (such as shared file descriptors) that traditional network file systems don't support, as well as implement them in a way that scales (e.g., shard a directory across servers to allow concurrent operations in that directory). Hare achieves this goal through a combination of new protocols (including a 3-phase commit protocol to implement directory operations correctly and scalably) and leveraging properties of non-cache-coherent multiprocessors (e.g., atomic low-latency message delivery and shared DRAM). An evaluation on a 40-core machine demonstrates that Hare can run many challenging Linux applications (including a mail server and a Linux kernel build) with minimal or no modifications. The results also show these applications achieve good scalability on Hare, and that Hare's techniques are important to achieving scalability.Quanta Computer (Firm

Building a robust software-based router using network processors

ABSTRACT Recent efforts to add new services to the Internet have increased in-terest in software-based routers that are easy to extend and evolve. This paper describes our experiences using emerging network pro-cessors--in particular, the Intel IXP1200--to implement a router. We show it is possible to combine an IXP1200 development boardand a PC to build an inexpensive router that forwards minimumsized packets at a rate of 3:47Mpps. This is nearly an order ofmagnitude faster than existing pure PC-based routers, and sufficient to support 1:77Gbps of aggregate link bandwidth. At lesser aggre-gate line speeds, our design also allows the excess resources available on the IXP1200 to be used robustly for extra packet process-ing. For example, with 8 \Theta 100Mbps links, 240 register operationsand 96 bytes of state storage are available for each 64-byte packet